Protection schemes involve encoding redundant information with data for transmission or storage, and later checking that the data and redundant information are consistent. Numerous protection schemes are well known, including triplication, parity, error correction codes (ECC), and 8b10b encoding. Protection schemes apply to any of source data, addresses, packet headers, and other useful transferred information, all of which are data in the context of adding redundant information.
Different protection schemes have different amounts of redundant information, such as two bits per bit of data for triplication, one bit per byte of data for per-byte parity, one bit per multi-byte word of data for per-word parity, four bits per byte of data for per-byte ECC providing a protection level of single error correction (SEC), or five bits per byte of data for per-byte ECC providing a protection level of single error correction and double error detection (SECDED). A byte is eight bits. FIG. 1 shows a table of the number of bits of redundant information needed to provide SEC ECC and SECDED ECC for ranges of numbers of data bits.
Systems-on-chips (SoCs) are designed with hardware description language (HDL) code. Verilog, SystemVerilog, very high-speed integrated circuit hardware description language (VHDL), and SystemC are HDLs.
Some applications of SoCs, such as automobile safety systems, industrial automation equipment, and data centers require that on-chip data, processing, storage, and communication functions are error resilient. That means that they if their physical structures wear out over time or they have manufacturing defects or they are impacted by alpha particle radiation that causes data to become corrupted, that corruption will be detected or detected and corrected.
Modern SoCs include semiconductor intellectual property (IP) cores, integrated in communication with each other, to perform different useful functions. Some common IPs are central processing units (CPU)s, dynamic random access memory (DRAM) controllers, static random access memory (SRAM) buffers, graphics processing units (GPU)s, and direct memory access (DMA) engines. Most modern SoCs connect the IPs using an interconnect IP. Some common types of interconnects are crossbars, networks-on-chip (NoC)s, and meshes. SoC designers often procure such IPs from third-party IP vendors who provide HDL source code.
IPs designed for SoCs for error resilient applications use parity or ECC or other types of protection schemes. However, different IPs use different protection schemes. For example a CPU master IP, such as the 32-bit ARM R5 CPU, can uses 32-bit SECDED ECC scheme and a 128-bit Flash memory controller can use a 128-bit SECDED ECC scheme. What is needed is a way for the two to be properly connected in an SoC. Furthermore, what is needed is a way to make an interconnect IP configurable as HDL code in order to provide for connecting IPs with inherently incompatible protection schemes.